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Clock Generators for SOC Processors: Circuits and Architectures

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Product Overview
Specifications
PublisherSpringer; Softcover reprint of hardcover 1st ed. 2005 edition
ISBN 139781441954701
ISBN 101441954708
AuthorAmr Fahim
Book FormatPaperback
LanguageEnglish
Book DescriptionPhase-Locked Loop Fundamentals.- Low-Voltage Analog Cmos Design.- Jitter Analysis in Phase-Locked Loops.- Low-Jitter PLL Architectures.- Digital PLL Design.- DSP Clock Generator Architectures.- Design for Testability in PLLs.- Clock Partitioning and Skew Control.
About the AuthorAmr M. Fahim received his B.A.Sc, M.A.Sc, and Ph.D degrees from the University of Waterloo in Computer Engineering in 1996 and Electrical Engineering in 1997 and 2000, respectively. In 2000 he joined Qualcomm Inc., where he is currently working on the development of mixed-signal designs.  He is the author of over 20 papers and 5 patents in this area, and has been a reviewer for the IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems II.
Publication Date5 November 2010
Number of Pages264 pages
Cart Total  534.00

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